Transistor performance in advanced nodes is increasingly limited by the contact resistance between the source/drain and the metal leading to the interconnect layers. For most metal/semiconductor interfaces, the contact resistance is dominated by the Schottky Barrier (SB) that forms at the interface. There have been several strategies to reduce the contact resistance by reducing the SB—e.g. reacted metals (silicides), workfunction tuning of the metal, Metal-Insulator-Semiconductor (MIS) structures, and the like.
These strategies have resulted in varying degrees of success. The fundamental problem with all of these approaches is there remains an abrupt interface between a material with an electronic energy gap and a metal. States with energies that are forbidden in bulk exist near the surface of materials with electronic energy gaps. Depending on the energy distribution of these states, dipoles form, which are responsible for SBs. The best reported values for interface contact resistivities are in the 10-9 ohm-cm2 range, and it is believed that for abrupt semiconductor-metal interfaces there is a fundamental limit to achieving ultra-low contact resistivities, so that the lowest values achievable (even in the absence of a SB) are in the 10E-10 ohm-cm2 range. Scaling dictates a factor of 2 decrease in feature area per node. Even with clever approaches to increase the effective contact area, the metal-semiconductor contact resistance will become the main limit to performance at a 3 nm node and beyond.
It would be desirable for a method and system that eliminate the large contribution of the abrupt metal/semiconductor interface to parasitic resistance, enabling further scaling without the performance penalties due to large contact resistance.